In the rapidly advancing semiconductor manufacturing industry, complementary metal oxide semiconductor (CMOS) FinFET devices are favored for many logic and other applications and are integrated into various different types of semiconductor devices. FinFET devices typically include semiconductor fins with high aspect ratios formed vertically with respect to a top surface of the substrate, and in which channel and source/drain regions of semiconductor transistor devices are formed. The fins are isolated, raised structures. A gate is formed over and along the sides of the fins, utilizing the advantage of the increased surface area of the channel and source/drain regions to produce faster, more reliable and better-controlled semiconductor transistor devices. One important advantage of FinFET technology is that the mismatch between the devices is significantly lower than that under conventional manufacturing processes.
A semiconductor memory chip such as static random-access memory (SRAM) includes a sense amplifier, wherein the sense amplifier is part of the read circuitry used to read data from the memory chip. The sense amplifier discriminates small differential signal to large signal (rail-to-rail signal) in order to sense the logic levels from a bitline pair (bitline and bitline bar), which represents a data bit (1 or 0) stored in a memory cell. The sense amplifier amplifies the small voltage swing to recognizable logic levels so that data can be interpreted properly at the output terminal of the memory cell.
The device mismatch of the sense amplifier affects how large the differential signal voltage can be sensed by the sense amplifier sensing (also referred to as sensing read margin, sensing margin also defined as minimum required differential voltage for a given sense amplifier).